Advances in semiconductor fabrication and manufacturing techniques have led to smaller, denser and more complex integrated circuits. Digital integrated circuits are spearheading the drive to increased densities and smaller geometries. At the same time digital integrated circuits are also being operated at higher speeds. The combination of increased density and higher speeds also results in increased power dissipation, which in turn increases the temperature of the device thereby reducing its reliability. Inorder to counteract the increased power dissipation modern devices are increasingly being designed to operate at reduced voltage levels. Current technology supports digital integrated circuits based on transistors with gate lengths reduced to 0.12u with corresponding supply voltages as low as 1.2V. However the IO requirements of digital integrated circuits are defined by the requirements of external devices and hence remain at voltage levels that are significantly higher than the core circuitry. Typical IO voltages remain at a 3.3 V to 5.0V level while the core circuitry operates at 1.2V. To operate in such an environment it is necessary to use voltage level translators, which translate signals at the lower voltage level of core logic to the higher lower voltage levels of the IO.
A transistor operating at a higher voltage such as 3.3V is designed to have a relatively long gate length to avoid punchthrough. At the same time, the transistor must also have a thicker gate oxide to prevent oxide break down. These transistors are relatively high voltage devices and are termed as 3.3V devices. If a 3.3V device is used for operation at lower voltage levels such as 1.2V, it provides relatively poor performance in term of speed owing to higher channel resistance and higher gate capacitance. In contrast, transistors operating at lower voltage levels are designed with shorter channel lengths to reduce the channel resistance and gate capacitance as the breakdown voltage requirements are lower. The lower resistance and gate capacitance enable significant increase in speed of operation besides providing higher density. Transistors which are used for lower voltages are low voltage devices and if designed for 1.2V operation are termed as 1.2V devices in the context of this document. Low voltage transistor models are not designed for use with higher voltages because of the risk of punchthrough and gate oxide breakdown.
To exploit the advantages of low voltage core logic and to make it compatible with the high voltage IO interface it is necessary to use a voltage level translator. While there are many techniques used to realize voltage level translators almost all of them produce voltage level translators that do not achieve equal rise and fall time under varying operating conditions resulting in the generation of unwanted glitches and delays.
Modern FPGAs utilize core voltages as low as 1.2 volts while IO voltage remains at 3.3 volts. Signals from the 1.2 volt core, if fed directly to circuitry working at higher voltage 3.3 volts will result in unnecessary power dissipation, since the 1.2 volt signal from the core logic will always keep the IO logic's PMOS transistor ON as its source is connected to 3.3 volts. To overcome this problem it is necessary to incorporate voltage translator circuitry that converts the 1.2 volts signal to 3.3 volts signal without any static power dissipation.
FIG. 1 shows a voltage translator according to the prior art as disclosed in U.S. Pat. No. 5,422,523. In this patent the low voltage input IN is fed to the gate of NMOS transistor 104 and also to the gate of a second NMOS transistor 103 through inverter LV. Inverter LV operates at a low voltage (VDDL). Transistors 103 and 104 are biased through transistors 101 and 102. The gate of transistor 102 is connected to the output OUT 1, while the gate of transistor 101 is connected to node 206. When IN rises from 0 volts to VDDL, NMOS transistor 104 is turned-on which reduces the voltage at node 206. This voltage reduction turns-on PMOS transistor 101 and increases the voltage at OUT 1. The output of LV at this time is 0 volts which turns-off NMOS transistor 103. The increase in voltage at OUT 1 reduces the conduction level of PMOS transistor 102 which further decreases the voltage at 206. This cycle is repeated until the voltage at OUT 1 rises to VDDH.
Similarly, when IN falls from VDDL to 0 volts, NMOS transistor 104 turns-off and NMOS transistor 103 turns-on, pulling down OUT 1 The reduction in voltage at OUT 1 turns-on PMOS transistor 102 slightly which in turn increases the voltage at node 206. This condition decreases the conductivity of PMOS transistor 101 leading to further reduction in the voltage at OUT 1. This recursive feedback ultimately reduces the voltage at OUT 1 to 0 volts.
The drawback with this approach is that it is difficult to achieve equal rise fall times under different operating conditions. This difficulty arises from unwanted capacitance effects which become more prominent at low voltages such as 1.2 volts. Also, since the difference between 1.2 volts and 3.3 volts is large the variations of various parameters with operating conditions has a pronounced effect on circuit performance.